In the first part of this blog (read here) we already figured out ways to optimize costs when switching from an FPGA to an ASIC-based design is an option. However, we also had to admit that there are still a large number of companies that will not hit a level of production volume that makes this decision easy. Now, we’ll introduce you to a game-changing Toshiba innovation that could make this decision a no-brainer!
Simplify ASIC Development Starting Your Project With Innovative Technologies
Due to the circumstance that transforming an FPGA into an ASIC usually results in high NRE and comes close to a full redesign of the FPGA this usually pays off only when high production volumes justify the investment. In this case reducing the unit price through a custom chip can be more important than keeping the development costs to a minimum.
For many companies this calculation is not that easy. It might be hard to predict the production volume over the next couple years, to make sure that there are no changes to design that would require a new ASIC or it might even be impossible to accurately estimate the development costs for an ASIC-based design.
Or even more common: Companies are struggling to take a decision because they are neither at the low production end nor the high volume end of the scale but somewhere in between where it is a decision that balances the necessary investment for an ASIC with its benefits (e.g. low power consumption, no start-up delay due to configuration, less cooling required).
In those cases developing an ASIC based on a special technology like the FFSA™ (Fit Fast Structured Array) from Toshiba can be a profitable alternative. FFSA™ devices use a silicon based “masterslice” which is common to all customers in combination with upper metal layers which are reserved for customization (see below).
This layout enables a proportion of the device masks to be prepared in advance, thus reducing both development and production time, and allows the largest part of the overall cost to be shared among many different customizations, resulting in much lower NRE than for individual ASIC development.
The key to this technology is a structure consisting out of a large amount of transistor-like cells (“sea of gates”). During the development of the ASIC these structures are connected with a single or multiple metal layers, wiring signal flow and clock distribution. This creates the configuration of the design.
By using ASIC development methodology and a cell library, FFSA™ performance and power consumption levels are nearly equivalent to those of ASICs. As the silicon basis is predesigned testing and qualification are also greatly simplified.
Moreover, with customization limited to only a few metal layers, turnaround time of sample manufacturing and mass production can be shorter than for ASICs.
In some devices, there are additional memory structures or layouts from other existing ASIC designs available which can be accessed through the configuration of the metal layers.
Taking it one step further, Toshiba’s FFSA™+ technology offers additional room for personalization of the devices as the application can be partially developed as ASIC which is then integrated as master in the silicon of the basic chip. Thus the ASIC part can be used for silicon-proven high performance design blocks while non-mature or logic which is subject to change can be realized in the metal-configurable FFSA™ structure.
This is especially attractive for applications in which an IP is reused in different platforms. The NRE for the development of the master occur just once and the costs for the development of the metal layers for the derivatives are reduced to a minimum.
Maximize Profit And Performance With Strategic Partnerships
In many cases similar structures are used to realize diverse applications. Therefore it makes sense to look for strategic partnerships in order to share the development costs for the ASIC.
An example is the development of communication interfaces together with strategic partners. The result would be a co-developed and co-financed master communication device which is then integrated into the own specific ASIC structure through the configuration of the metal layers.
EBV offers support during the search for strategic partners and further helps with the development of the custom technology within the EBVchips program. The requirements from customers across the whole EMEA region are collected and processed by EBV opening the door to a diverse platform of possible collaborations.