Transforming an FPGA into an ASIC is associated with high development cost and time. In many cases the lower unit price of ASIC-based designs still does not justify the higher development efforts. Therefore, designing an application specific chip is usually only rewarding for high volume production. However, there are strategies to minimize the NRE (non-recurring expenses) for ASICs as well as innovative technologies like Toshiba’s FFSA™ that dramatically increase the benefits of ASICs even in low to medium volume production.
ASIC Development Costs Can Be Influenced From Scratch
Consider this situation: You have a stable FPGA design and no changes have been necessary for a couple years. The volume meanwhile busted the 10.000 mark – now, does it make sense to develop an ASIC?
On the one hand the development costs can easily hit a couple millions. On the other hand there is a lot of potential to profit from an application specific chip through optimization of the NRE.
FPGA technology promises an easy transition to a customer specific ASIC. However, despite a lot of similarities within the technological features of FPGA and ASIC, during the conversion of an existing FPGA design into an ASIC a lot of limits are discovered that make this highly challenging or even impossible.
The reasons are diverse; examples for roadblocks could be the structures used by the FPGA manufacturer which cannot be copied by the ASIC provider as well as IPs which are either useless for the ASIC, need to be licensed or are protected and cannot be used due to legal restrictions.
If there is a good chance that an FPGA design will be transformed into a custom-chip project in the future there are a couple measures that can be taken during the initial FPGA-design to prepare the development process accordingly and to save efforts later.
The selection of IPs which have been tested and developed for diverse technologies offer the potential to immensely reduce trouble during the development of an ASIC.
In addition, licensing costs and restrictions should be considered. IPs are usually offered for free by FPGA manufacturers but are not transferable to other technologies in many cases.
Involving a potential ASIC manufacturer in the planning phase of a new design in order to align on IPs which can later be used for the custom chip as well as to investigate technological particularities which need to be considered during the development process further help to minimize the effort during the shift from FPGA design to ASIC design.
Optimize Costs By Looking At The Whole System
Peripherals like power supply, clock generation and interfaces contribute for a large portion of application costs. This is where ASICs offer additional potential to cut the costs.
The advantages of FPGAs, like high configurability and flexibility are usually important for prototyping and initial low volume production. However, in mature designs the disadvantages become obvious.
In most technologies a separate configuration flash is required for the FPGA which requires additional power and clocking. Initial programming of the flash memory adds also to the system cost.
Another drawback is the boot time as the FPGA is only functional after the configuration is loaded and checked. This start up delay depends on the system size and complexity.
An FPGA uses RAM-based configurable logic blocks (CLB) that are used to create and store the arbitrary combinatorial logic functions usually referred to as lookup tables (LUTs) as well as to route the logic within the block and to and from external resources.
These blocks are hardwired in an ASIC which means that the energy required to maintain the configuration in an FPGA is eliminated, significantly improving the power budget in an ASIC.
The power consumption is further reduced as in an ASIC the power distribution is hardwired as well and thus no unused regions are supplied with energy. (Editor’s note: Logically unused regions are not even realized in the silicon in an ASIC. However we will learn about technologies in which this process is of importance in the following).
While the CLB are realized in the silicon in FPGAs those configuration layers are made using metal in ASICs. The routing through I/O transistors creates effects like switching delays and power losses which are significantly lower in ASICs. Thus ASIC designs usually allow for higher clocking frequencies.
In practice it has been proven that the power consumption of a system can be reduced by a factor 5 through the application of ASICs instead of an FPGA-based solution. The associated cost for cooling can further be reduced by 50%. In combination with the elimination of the configuration RAM, the programming in the production, and the clocking improvements the system expenses are greatly reduced.
It is no secret that even with the measures described above the decision to switch to an ASIC design is not going to be an easy one. Especially if the production volume is not yet promising big numbers for the future. The good news is there are new technologies that sit in between FPGA and ASIC and deliver ultra-high customization capabilities while requiring less development time and costs than conventional ASICs. Read part two of this blog here to learn more about these innovations.