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Breaking The 1Tbps Barrier With UniBoard2

Recently several engineers broke the 1 Tbps barrier within the UniBoard2 project!

UniBoard2, an activtiy which is part of the RadioNet3 project aims to create a FPGA-based, generic, scalable, high-performance computing platform for radio-astronomical applications. The innovative re-designed second generation builds upon the experience obtained through the UniBoard project and will be ready for the next generation of astronomical instruments (notably the SKA), at the end of 2015.

Lately several engineers pushed the boundaries of what’s possible breaking the 1 Tbps barrier with the UniBoard2 and submitted the picture of the victorious team behind the success to the ASTRON JIVE Daily Image (AJDI) archive. AJDI is a family chronicle of the sister institutes ASTRON and JIVE that proudly presents their scientific and technical successes and the people behind them.

UNB2_ALTERA

From left to right, the victorious team consists of: Leon Hiemstra (firmware engineer Astron), Karl de Boois (Field Application Engineer EBV), Gijs Schoonderbeek (hardware design Astron), Peter Schepers (transceiver specialist Altera) and Jonathan Hargreaves (firmware engineer JIVE). image: AJDI

The Submitters of the picture above, Leon Hiemstra, Jonathan Hargreaves and Gijs Schoonderbeek write in the description: 

Engineering is about pushing the envelope. With UniBoard2 we wanted to break the Tbps barrier(*), and that is exactly what we have done.

 

During a visit by Peter Schepers from Altera Inc. and Karl de Boois from EBV, the nitty-gritty details of their transceivers where explained to us. Within a week after that, we breached the 1Tbps barrier. This was done(**) by using twenty-four 10Gbps transceivers on the backplane side of the board for each FPGA (making in total 960 Gbps full duplex), and twenty-four optical interconnections on the front side per node (making in total 960Gbps). Although we were the first to use the Arria10 FPGAs from Altera, we were able to achieve error rates smaller than 1E-13 (one error per 10 Tbits). Last week, we were able to run all 96 transceivers for a single node (almost 1Tbps per node). This will be the target for all FPGAs on the production boards by the end of the year.

 

(*) One Terabit per second (Tbps) is 1.000.000.000.000 bps, or 100.000 HDX 1080p video streams. The aggregated traffic on all AMS-IX (Amsterdam Internet Exchange) connected network ports has a peak of 3.7 Tbps, which can be handled by a single UniBoard2 when all 384 transceivers are used.
(**) We do not apologize about the jargon. It just says it all.

 

We send huge congratulations to everyone involved and look forward to new and exciting break-throughs!