Guest blog from Giles Peckham
Application software developers are demanding ever increasing levels of performance from the platforms they run on to support more complex applications and increasing volumes of data. For edge and cloud-based applications the trend is towards using programmable logic in the form of All Programmable FPGAs or Heterogeneous SoCs, which offer the developer significant acceleration capabilities. These devices have traditionally been accessible only to hardware designers but of course application software developers want a software development environment and ecosystem that supports both industry standard high-level libraries and frameworks such as those used in computer vision and machine learning, for example OpenCV, OpenVX, FFmpeg and Caffe.
The core technology enabling application developers to leverage the potential of programmable logic is high level synthesis (HLS). HLS enables algorithms specified in C, C++ or OpenCL to be accelerated in programmable logic directly. To maximise design productivity, the HLS tool should be part of a development tool chain and ecosystem which supports high-level frameworks and libraries.
For application developers targeting Xilinx cloud-based FPGA applications or edge-based heterogeneous SoC applications, there exist two such development tool chains: SDAccel™ and SDSoC™ for cloud- and edge-based developments respectively. Application developers use SDSoC when targeting All Programmable Zynq®-7000 SoC or Zynq® UltraScale+™ MPSoC system on chip families, while SDAccel on the other hand is used when the application developer wishes to target UltraScale+ FPGAs.
SDAccel and SDSoC feature supporting ecosystems complete with acceleration stacks, which enable the acceleration of frameworks and library functions into programmable logic. These are the Reconfigurable Acceleration Stack (RAS) for cloud-based applications, and the reVISION™ stack for edge-based embedded vision applications.
Both the RAS and reVISION stacks are organised in three distinct layers, very similar to the OSI seven-layer model. The lowest platform layer defines the underlying hardware and its interfaces. It is the second layer of both stacks where the acceleration occurs, with acceleration support of OpenCV and Caffe within reVISION, while RAS provides acceleration support for Caffe, integration with SQL environments, and support for MPEG processing using FFmpeg. The third layer of both stacks is used to complete the high-level application which leverages the accelerated layer. This enables the RAS to provide support for OpenStack allowing integration with the server architecture, while reVISION uses industry-standard frameworks to create the overall application required for the solution.
For the application developer, as well as the performance increase which comes with the use of these stacks, there are several further additional benefits. Programmable logic also delivers an any-to-any interfacing capability, the flexibility to adapt to the latest standards and revisions, and the most efficient processing power per watt.
One example which demonstrates the acceleration provided by combining UltraScale+ FPGAs and the cloud, is the recent announcement from the Children’s Hospital of Philadelphia (CHOP) and Edico Genome. CHOP and Edico Genome have recently set a new scientific world record for rapidly processing whole human genomes into data files useable for researchers (link). 1000 paediatric genomes were processed through Edico Genome’s DRAGEN Genome Pipeline in two hours and 25 minutes. This achievement was made possible thanks to cloud-based acceleration using high performance All Programmable FPGAs available via Amazon Web Services’ EC2 F1 Instance.
For the first time, application developers at both the edge and within the cloud are now able to leverage the benefits of programmable logic using industry standard frameworks and libraries, thanks to the combination of development tools like SDAccel and SDSoC with the RAS and reVISION stacks. If you are an application software developer, why not come along to the Xilinx Developer Forum in Frankfurt on 9th January 2018, to learn how you too can accelerate your development. To learn more and register: https://www.xilinx.com/products/design-tools/developer-forum.html
Giles has more than 30 years’ experience in the semiconductor industry, starting with the design of ASSPs for consumer applications at Philips Semiconductors (now NXP) before moving on to FAE and marketing roles for gate array and standard cell products and finally a sales role in the same organisation. After five years in IP product marketing and international sales roles at European Silicon Structures, the e-beam direct-write ASIC company, Giles recognised the increasing potential for FPGAs and joined Xilinx. Whilst at Xilinx, he has held a number of technical and commercial marketing roles in EMEA before being promoted to run the group. Giles holds a BSC in Electronic Engineering and Physics from Loughborough University, UK and a Professional Postgraduate Diploma in Marketing from the Chartered Institute of Marketing in the UK. Giles is based in the Xilinx EMEA office in London.