Guest Blogs Industry 4.0 Internet of Things

Time-Sensitive Networking (TSN): Converging networks for Industry 4.0

Xilinx Time Sensitive Networking

Guest blog from Michael Zapke

One of the major challenges faced by Industry 4.0 applications is converging the Information Technology (IT) and Operational Technology (OT) networks. Converged networks enable end-to-end communication from field devices like drives and sensors all the way up to workstations for the Enterprise Resource Planning (ERP) system.  However, many current industry applications use separate networks, requiring gateways and bridges to connect the IT and OT networks.

This separation of networks occurs as OT networks need to support real-time deterministic communications and demonstrate a low packet delay variation, while IT networks are optimized for high bandwidth, flexible topologies and automated configuration. Unfortunately, separate networks are difficult to scale, require multiple protocols, need network engineering before installation and often have bandwidth restrictions in OT segments.

Converging the IT and OT networks addresses these issues, providing a network that is no longer strongly hierarchical nor limited in scalability or performance, along with achieving the desired vertical integration as previously identified.

The key to aligning these networks is provided by Time Sensitive Networking (TSN). TSN is a set of IEEE 802 sub-standards which, when implemented, enable deterministic communication over Ethernet networks.

TSN enables different classes of network traffic to share the same link, providing both network management and a reserved path for scheduled traffic, ensuring deterministic communications. As such, TSN enables one common network to be implemented, supporting multiple communication standards.

Time awareness across the network is implemented in TSN by allocating scheduled traffic in time-defined slots, while also supporting cyclic data transmission and providing pre-emption for higher priority packets.

Time Sensitive Networking (TSN) is defined by extensions to the Ethernet standards IEEE 802.1 and IEEE 802.3. Not all TSN-related substandards are adopted already today (status Oct 2017). Examples for standards in draft stage are Synchronisation (P802.1AS-Rev) and Seamless Redundancy (P802.1CB).

IEEE Time Sensitive Networking Standards
Figure 1-IEEE TSN Standards

Correctly implementing TSN requires a solution which can provide a low latency and deterministic response at TSN endpoints and switches. The accurate timing for the transmission of scheduled Ethernet Frames requires dedicated circuitry like FPGAs provide them. As such, the Xilinx® Zynq®-7000 and Zynq® UltraScale+™ MPSoC devices provide ideal single chip solutions.

Implementing TSN using Xilinx’s 100M/1G TSN Subsystem LogiCORE IP within a Zynq-7000 or Zynq UltraScale+ MPSoC device utilises both the Processing System (PS) and the Programmable Logic (PL). The LogiCORE IP consists of FPGA logic for MAC, TSN Bridge and TSN Endpoint, along with software components for network synchronization, initialization, and for interfacing with network configuration controllers for stream reservation as defined in P802.1Qcc. The software is designed to run on Linux and will be published as Yocto patches supported by Xilinx’s PetaLinux toolset.

The TSN Subsystem LogiCORE IP provides deterministic behaviour in the PL for synchronization (IEEE 802.1AS), scheduled traffic (IEEE 802.1Qbv), and seamless redundancy (P802.1CB), along with helping to offload the processing unit. It is also possible to implement an optional integrated time-aware L2 switch enabling either chain or tree topology.

Xilinx Time Sensitive Networking implementation within a Zynq
Figure2- TSN implementation within a Zynq-7000 or Zynq UltraScale+ MPSoC

Once instantiated internally, the TSN Subsystem LogiCORE IP core provides individual interfaces for each traffic class and these are used in conjunction with the embedded Processing System. Up to three AXI Stream interfaces are configurable at the IP core, one for the class “scheduled traffic”, one for “reserved traffic” and one for Best Effort. An additional AXI Lite interface is used for initialisation and configuration of the components of the TSN Subsystem. Figure 3 shows how the TSN Subsystem LogiCORE IP is typically used in a Programmable SoC.

Xilinx TSN Subsystem LogiCORE IP supports Ethernet with 100 Mbit/s (Fast Ethernet) and 1000 Mbit/s (Gigabit Ethernet).

Xilinx Time Sensitive Networking Detailed Architectural Implementation
Figure 3 – TSN Detailed Architectural Implementation with Zynq UltraScale+ MPSoC

With the majority of the TSN networking implemented within Programmable Logic, it provides not only the determinism and low latency required by the TSN standards, but, because Programmable Logic is re-configurable through netlist download to the device, it also provides the ability to update the TSN Subsystem LogiCORE IP Core as the TSN standards progress through the working and task groups and revisions are introduced.

Wrapping up

To enable deployment of Industry 4.0 applications, there needs to be convergence between IT and OT networks. TSN provides the ability to converge these networks, offering significant advantages in network connectivity, scalability and cost of deployment and ownership. Implementing TSN within an All Programmable Zynq-7000 or Zynq UltraScale+ MPSoC device provides the user with a single chip solution, which can also provide the processing capability in the PS and PL to perform the IIoT applications between Edge and Cloud.

Xilinx’s Time Sensitive Networking (TSN) has been released with the name 1G/100M TSN Subsystem LogiCORE IP in May 2017 for early access customers and will continue the rollout in Q4/2017.

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Xilinx will showcase Time Sensitive Networking at this year’s SPS IPC Drives trade fair, which will take place from 28 – 30 November 2017 in Nuremberg/Germany. The leading exhibition for electric automation will have a strong focus on Industry 4.0 and digital transformation.

Author Bio:

Michael Zapke is Product Marketing Manager for Industrial Applications at Xilinx in Munich, Germany. He has more than 25 years of experience in R&D and PLM roles, among others as Project Manager for large-scale ASIC and FPGA designs, Head of Systems Engineering for Telecom infrastructure equipment and Product Marketing Manager for Industrial Communication. Since 2013, he shapes innovations for industrial applications on All Programmable devices from Xilinx in close cooperation with leading companies and research institutes. Michael represents Xilinx in TSN-related alliances and is responsible for the recently released TSN LogiCORE product.