Embedded system developers are increasingly challenged to present solutions which offer superior performance, connectivity and security, while still providing the most power efficient solution. To address these challenges developers are leveraging the capabilities provided by Xilinx® All Programmable devices. These devices are available as Field Programmable Gate Arrays (FPGA) which are programmable logic based or heterogeneous System on Chips (SoC) which combine high performance ARM® cores with programmable logic.
Programmable logic has come a long way since the invention of the first FPGA in 1984 by Xilinx. The first device, the XC2064, released in 1985 was much smaller than today’s devices, with only 64 flip flops and 128 3-input look up tables. It was therefore not able to address the entire problem space, instead being used as glue logic. Xilinx knew that Moore’s law and process scaling would dictate that both transistors and interconnect would get much cheaper, enabling a rapid increase in capabilities. This enabled a rapid increase in FPGA capacity and capability throughout the 1990’s and early 2000’s. However, to be able to address the entire problem space, FPGAs needed to provide more than just programmable logic, and mid-2000 saw the introduction of the platform FPGA. This fused programmable logic with dedicated processors, memory interfaces and functionality such as DSP units, clock management and Giga Bit transceivers, enabling the user to address the entire problem within a single device. Today, these devices have evolved into the heterogeneous SoC we see in the All Programmable Zynq®-7000 SoC and Zynq® UltraScale+™ MPSoC families, and soon in the RFSoC devices.
One of the use cases which best demonstrates the benefits of all programmable devices is within the embedded vision sphere. Currently, over 290 suppliers are partnering with Xilinx across a range of embedded vision applications including ADAS, Pro AV, Industrial Vision, Smart Cameras and Drones. Many of these partners are using the All Programmable Zynq-7000 SoC or Zynq UltraScale+ MPSoC. These devices enable implementation of the image processing pipeline within the programmable logic, removing traditional bottlenecks seen in a CPU/GPU based approach, while the high-level decision making, system management and communication is performed by the ARM processors. In many applications such as autonomous vision guided robotics the application will also leverage machine learning inference to classify and detect objects.
The traditional method of developing image processing pipelines and machine learning inference is to develop a high-level algorithmic model before re-creating this model using an HDL. This increases the design time, non-recurring costs, and introduces risk ensuring the implemented design performs the same as the high-level model.
This is where the reVISION™ stack from Xilinx demonstrates its significant advantage enabling software defined development of All Programmable Zynq SoC and Zynq MPSoC devices within SDSoC™. SDSoC is a system optimising compiler which enables the development of the entire system using C, C++ or OpenCL®. This is possible due to SDSoC’s combination of Vivado® High Level Synthesis with a connectivity framework, which enables seamless movement of functions between the processor cores and the programmable logic. Of course, moving functions into the programmable logic comes with a significant performance boost.
reVISION, therefore, enables the developers to use industry standard high-level frameworks and libraries like OpenCV, OpenVX and Caffe to implement the image processing algorithm and machine learning inference. At the same time, developers can obtain performance increases by moving these functions into the programmable logic.
This ability to exploit the programmable logic within reVISION is due to the fact that several OpenCV functions (including the OpenVX core) and machine learning elements such as Convolution and Pooling are optimised for acceleration in the programmable logic.
Leveraging this acceleration enables a more responsive and power efficient solution providing up to 42x frames per second per watt increase for image processing, or up to 6x images per second per watt increase for machine vision applications.
This combination of all programmable devices, system optimising compliers and reVISION enables the development of a more responsive, power efficient and secure solution. It also removes the need to be an HDL specialist to leverage the capabilities of programmable logic.
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